Mehmet Aslan

Mehmet Aslan

Portland, Oregon Metropolitan Area
3K followers 500+ connections

About

Most people I know dislike change. I, however, embrace it. And as an engineer in…

Activity

Join now to see all activity

Experience

  • Tektronix Graphic

    Tektronix

    Beaverton, Oregon

  • -

    San Francisco Bay Area

  • -

    Santa Clara, California

  • -

    San Francisco Bay Area

  • -

Education

Volunteer Experience

  • Fortive Graphic

    Fortive Day of Caring Volunteer

    Fortive

    - Present 7 years

    Fortive (Tektronix's parent company) gives back to their employees’ communities in a through the annual Fortive Day of Caring, where employees receive one paid day that to use as a day to serve a cause or charity of their choice

  • Tektronix Graphic

    Tektronix Foundation Supporter

    Tektronix

    - Present 7 years

    The Tektronix Foundation provides charitable support through this private foundation funded each year with a portion of the Company's profits.

Publications

  • A 101 dB DR 1.1 mW audio delta-sigma modulator with direct-charge-transfer adder and noise shaping enhancement

    IEEE, Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian

    A low-power audio delta-sigma modulator (DSM) is presented. Two new techniques are proposed to reduce the overall power dissipation of the modulator: a power-efficient direct-charge-transfer adder is employed, and noise-shaping enhancement is implemented by feeding the differentiated quantization noise to the input of the second integrator. The measured power dissipation is 1.1 mW, the dynamic range is 101.3 dB, the spur-free dynamic range is 112 dB and the signal-to-noise-plus-distortion ratio…

    A low-power audio delta-sigma modulator (DSM) is presented. Two new techniques are proposed to reduce the overall power dissipation of the modulator: a power-efficient direct-charge-transfer adder is employed, and noise-shaping enhancement is implemented by feeding the differentiated quantization noise to the input of the second integrator. The measured power dissipation is 1.1 mW, the dynamic range is 101.3 dB, the spur-free dynamic range is 112 dB and the signal-to-noise-plus-distortion ratio is 99.3 dB. The power efficiency of this design is among the best in DSMs with high (over 15) ENOBs.

    Other authors
    See publication
  • 82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction

    IEEE, Custom Integrated Circuits Conference (CICC), 2010 IEEE

    A third-order multi-channel incremental ADC with a 5-level quantizer is presented. An optimal decimation filter is used which minimizes the weighted sum of the thermal and quantization output noises. Digital correction is used to suppress mismatches in the multi-bit DAC. The prototype obtained a signal-to-noise-and-distortion ratio of 81.5 dB, within a total of 21.7 kHz signal bandwidth at a 10 MHz sampling frequency. The total power consumption for 20 channels is 6.7 mW.

    See publication
  • Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections

    IEEE, Custom Integrated Circuits Conference, 2007. CICC '07

    A novel second order sigma delta modulator (SDM) with 5-bit quantizer has been proposed with simplified DAC arrays, high-order truncation noise shaping for increased tolerance to analog imperfections, and extended dynamic range for a maximum input signal swing of up to -0.45 dBFS. With truncation filter and pseudo SDM in the DSP, the truncation and saturation errors are compensated through the DAC arrays and the DSP. The design was fabricated in 0.18mu dual gate oxide (DGO) process. A SNDR…

    A novel second order sigma delta modulator (SDM) with 5-bit quantizer has been proposed with simplified DAC arrays, high-order truncation noise shaping for increased tolerance to analog imperfections, and extended dynamic range for a maximum input signal swing of up to -0.45 dBFS. With truncation filter and pseudo SDM in the DSP, the truncation and saturation errors are compensated through the DAC arrays and the DSP. The design was fabricated in 0.18mu dual gate oxide (DGO) process. A SNDR (signal-to-noise-and-distortion ratio) of 98.4 dB and a SNR (signal-to-noise ratio) of 108-dB were measured for a 31.25-KHz signal bandwidth at 8-MHz sampling frequency with a power consumption of about 14.7 mW.

    See publication
  • Reliable Decentralized Stabilization of Linear Plants

    University of California, Davis

    Book published from Thesis:

    Reliable stabilization of linear time-invariant multi-input/multi-output plants is considered using a two-channel decentralized controller configuration. Necessary and sufficient conditions are obtained for existence of reliable controllers that maintain stability under the possible failure of either one of the two controllers. All decentralized controllers that achieve reliable stabilization are characterized.

    See publication

Patents

  • Low noise, high CMRR and PSRR input buffer

    Issued US 8,330,537

    A rail-to-rail buffer receiving a differential input signal and generating a differential output signal includes first and second amplifier circuits configured in a pseudo differential buffer structure and first and second comparators coupled to compare the respective part of the differential input signal and a first voltage and to generate select signals. Each of the first and second amplifier circuits includes first and second complementary differential input stages and the first and second…

    A rail-to-rail buffer receiving a differential input signal and generating a differential output signal includes first and second amplifier circuits configured in a pseudo differential buffer structure and first and second comparators coupled to compare the respective part of the differential input signal and a first voltage and to generate select signals. Each of the first and second amplifier circuits includes first and second complementary differential input stages and the first and second comparators generate respective select signals to turn on only one of the first or the second differential input stage in each amplifier circuit depending on a value of the respective part of the differential input signal. In operation, the first and second complementary differential input stages of each amplifier circuit not being turned on at the same time.

    See patent
  • Beta Variation Cancellation in Temperature Sensors

    Issued US 8,021,042

    An apparatus and method for canceling variations in the beta for a bipolar junction transistor so that the diode equation can be employed to accurately measure the temperature of the transistor based at least in part on a ratio of two target collector currents and two measurements of the base-emitter voltage of the transistor. If the determined collector current of the transistor is relatively equivalent to one of the first and second target collector currents, the transistor's base-emitter…

    An apparatus and method for canceling variations in the beta for a bipolar junction transistor so that the diode equation can be employed to accurately measure the temperature of the transistor based at least in part on a ratio of two target collector currents and two measurements of the base-emitter voltage of the transistor. If the determined collector current of the transistor is relatively equivalent to one of the first and second target collector currents, the transistor's base-emitter voltage is measured and stored. An analog feedback circuit can be employed to change the determined collector current to be relatively equivalent to the first and second target collector currents. The analog feedback circuit can include an optional sample and hold component to further reduce power consumption and reduce noise. A digital circuit can be employed to change the determined collector current to be relatively equivalent to the first and second target collector currents. Additionally, the transistor can be remotely located in another integrated circuit.

    See patent
  • Method and Device for White Level Calibration

    Issued US 7,889,251

    Calibrating a white level in an image scanning device. A target white level is accessed. A high white level is determined for pixel data output by an amplifier. A gain adjustment to the amplifier is determined to correct a portion of an error between the target white level and the high white level. The gain adjustment is applied to the amplifier.

    Other inventors
    See patent
  • Three-terminal dual-diode system for fully differential remote temperature sensors

    Issued US 7,828,479

    A three-terminal, dual-diode system is compatible with both fully differential remote and single-ended remote temperature measurement systems. Fully differential remote temperature sensor systems offer better noise immunity and can perform faster conversions with less sensitivity to series resistance than single-ended systems. The two diode system can be used with either fully differential or single-ended temperature measurement systems, which can be used when upgrading from a single-ended…

    A three-terminal, dual-diode system is compatible with both fully differential remote and single-ended remote temperature measurement systems. Fully differential remote temperature sensor systems offer better noise immunity and can perform faster conversions with less sensitivity to series resistance than single-ended systems. The two diode system can be used with either fully differential or single-ended temperature measurement systems, which can be used when upgrading from a single-ended architecture to a fully differential architecture, and which can provide backwards compatibility to single-ended architectures for users of fully differential architectures. The simultaneous forwards and backwards compatibilities reduces development risk associated with switching from a proven architecture (e.g., single-ended) to a newer, less-proven, architecture (e.g., fully differential).

    Other inventors
    See patent
  • Capacitor rotation method for removing gain error in sigma-delta analog-to-digital converters

    Issued US 7,825,838

    A method for removing component mismatch errors for a system parameter being set by a ratio of two or more physical, electrical components (“components”) of the same kind on an integrated circuit including providing an array of component units having the same component value, determining the actual component values of each component unit in the array, selecting component units based on the actual component values to form pairs of component units where the pairs have approximately the same total…

    A method for removing component mismatch errors for a system parameter being set by a ratio of two or more physical, electrical components (“components”) of the same kind on an integrated circuit including providing an array of component units having the same component value, determining the actual component values of each component unit in the array, selecting component units based on the actual component values to form pairs of component units where the pairs have approximately the same total component values, ordering the component unit pairs, assigning alternate component unit pairs to be associated with each of the two or more components, rotating at a first frequency the assignment of the component unit pairs. At each rotation, the component unit pairs to be associated with each component are shifted so that each component unit pair is associated with a different one of the two or more components in turn.

    See patent
  • Background calibration method for analog-to-digital converters

    Issued US 7,825,837

    A method for calibrating an analog-to-digital converter includes sampling an analog input signal and generating input samples, reversing the polarity of at least one input sample, averaging the digital output codes associated with a first pair of input samples where the first pair of input samples has opposite polarities, and generating an offset correction value being the average of the digital output codes associated with the first pair of input samples. In another embodiment, a method for…

    A method for calibrating an analog-to-digital converter includes sampling an analog input signal and generating input samples, reversing the polarity of at least one input sample, averaging the digital output codes associated with a first pair of input samples where the first pair of input samples has opposite polarities, and generating an offset correction value being the average of the digital output codes associated with the first pair of input samples. In another embodiment, a method for calibrating an ADC includes sampling the analog input signal and generating input samples, introducing an incremental value to modify the magnitude of at least one input sample, computing an actual gain value using the digital output codes associated with a first input sample and a second input sample having the modified magnitude, and generating a gain correction value being the ratio of an ideal gain of the ADC to the actual gain.

    See patent
  • Beta Variation Cancellation in Temperature Sensors

    Issued US 7,766,546

    An apparatus and method for canceling variations in the beta for a bipolar junction transistor so that the diode equation can be employed to accurately measure the temperature of the transistor based at least in part on a ratio of two target collector currents and two measurements of the base-emitter voltage of the transistor. If the determined collector current of the transistor is relatively equivalent to one of the first and second target collector currents, the transistor's base-emitter…

    An apparatus and method for canceling variations in the beta for a bipolar junction transistor so that the diode equation can be employed to accurately measure the temperature of the transistor based at least in part on a ratio of two target collector currents and two measurements of the base-emitter voltage of the transistor. If the determined collector current of the transistor is relatively equivalent to one of the first and second target collector currents, the transistor's base-emitter voltage is measured and stored. An analog feedback circuit can be employed to change the determined collector current to be relatively equivalent to the first and second target collector currents. The analog feedback circuit can include an optional sample and hold component to further reduce power consumption and reduce noise. A digital circuit can be employed to change the determined collector current to be relatively equivalent to the first and second target collector currents. Additionally, the transistor can be remotely located in another integrated circuit.

    See patent
  • Matching for Time Multiplexed Transistors

    Issued US 7,541,861

    Other inventors
    • Dan D'Aquino
    See patent
  • Matching for Time Multiplexed Resistors

    Issued US 7,449,943

    Other inventors
    See patent
  • Short Circuit Protection

    Issued US 7,031,127

    Other inventors
    See patent
  • Output Buffer

    Issued US 6,992,512

    Other inventors
    See patent
  • Fan speed detection in the presence of PWM speed control

    Issued US 6,778,938

    Other inventors
    See patent
  • Dual Threshold Buffer with Hysteresis

    Issued US 6,774,676

  • Nonlinear Fan Control

    Issued US 6,757,592

  • Fan Acceleration Control

    Issued US 6,737,824

  • Direct temperature sensing of a semiconductor device

    Issued US 6,149,299

    Other inventors
    See patent

Honors & Awards

  • National Semiconductor Patent of the Year Award

    National Semiconductor

    Award given for the invention that has achieved product, revenue and innovation milestones across the company

  • Bronze Medal, 30th Mathematics Olympiad, Braunschweig, Germany

    IMO

    3rd place and bronze medal in the most prestigious international mathematics competition for high school students representing Turkey.

Languages

  • English

    Native or bilingual proficiency

  • Turkish

    Native or bilingual proficiency

Organizations

  • Industry Advisory Board Executive Committee

    School of Electrical Engineering Computer Science, Oregon State University

    - Present

    I provide guidance on the university’s electrical engineering computer science program by reviewing strategic plans, the curriculum, and budget.

Recommendations received

More activity by Mehmet

View Mehmet’s full profile

  • See who you know in common
  • Get introduced
  • Contact Mehmet directly
Join to view full profile

Other similar profiles

Explore collaborative articles

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

Explore More

Others named Mehmet Aslan in United States

Add new skills with these courses